Belles Ondes : Creative Engineering

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This section describes how patch Data is encoded, and stored in ROM.

Start	Stop	Name	Comment
0x00	0x0C	Header	SIDaster Synth Header
0xD	0x32	Patch1	Patch #1
0x32	0x57	Patch2	Patch #2
0x57	0x7C	Patch3	Patch #3
0x7C	0xA1	Patch4	Patch #4
0xA1	0xC6	Patch5	Patch #5
0xC6	0xEB	Patch6	Patch #6
0xEB	0X110	Patch7	Patch #7
0x110	0X135	Patch8	Patch #8

Used to store generic Data in the ROM. Start adress is 0x00.

Adress(Dec)	(Hex)	Name	Comment
0	00	'S'	“SIDaster” String
1	01	'I'
2	02	'D'
3	03	'a'
4	04	's'
5	05	't'
6	06	'e'
7	07	'r'
8	08	Version	Byte : the version of the SIDaster presets installed
9	09	Spare 1	Spares
10	0A	Spare 2
11	0B	Spare 3
12	0C	Spare 4

Every SIDaster patch is a succession of 38 Bytes organised as shown below

Category	Adress(Dec)	(Hex)	Name	Comment
Synth	0	00	Name LSB	Patch Name (4 Bytes long)
	1	01	Name MSB	Patch Name (4 Bytes long)
	2	02	Mode	Synth Mode
Osc1	3	03	Wave1	Osc1 Wave
	4	04	Coarse1	Osc1 Coarse
	5	05	Fine1	Osc1 Fine Frequency
	6	06	Coarse1	Osc1 Coarse
	7	07	PW1 LSB	Osc1 PWM
	8	08	PW1 MSB	Osc1 PWM
	9	09	Ctrl1	Osc1 Control Byte
	10	0A	AD1	Osc1 Attack & Decay
	11	0B	SR1	Osc1 Sustain & Release
Osc2	12	0C	Wave2	Osc2 Wave
	13	0D	Coarse2	Osc2 Coarse
	14	0E	Fine2	Osc2 Fine Frequency
	15	0F	Coarse2	Osc2 Coarse
	16	10	PW2 LSB	Osc2 PWM
	17	11	PW2 MSB	Osc2 PWM
	18	12	Ctrl2	Osc2 Control Byte
	19	13	AD2	Osc2 Attack & Decay
	20	14	SR2	Osc2 Sustain & Release
Osc3	21	15	Wave3	Osc3 Wave
	22	16	Coarse3	Osc3 Coarse
	23	17	Fine3	Osc3 Fine Frequency
	24	18	Coarse3	Osc3 Coarse
	25	19	PW3 LSB	Osc3 PWM
	26	1A	PW3 MSB	Osc3 PWM
	27	1B	Ctrl3	Osc3 Control Byte
	28	1C	AD3	Osc3 Attack & Decay
	29	1D	SR3	Osc3 Sustain & Release
SID Control	30	1E	Freq LSB	Filter Cutoff Frequency
	31	1F	Freq MSB	Filter Cutoff Frequency
	32	20	Res	Resonnance and Filter input
	33	21	Mode	Filter Mode and Main Volume
Spare	34	22	Spare1	Spare
	35	23	Spare2
	36	24	Spare3
	37	25	Spare4